R&D Projects


DEMETER Project

R&D Projects


DEMETER Project

DEMETER stands for DEep SubMicron System-on-Chip (SoC) for Harsh Environment applicaTions using EuRopean Technologies

The main part of the project is for ST to provide a radiation hardened FPGA and a multicore ARM based SoC with eFPGA in 28nm or beyond.

The European Space Community needs high complexity radiation-hardened reprogrammable FPGAs allowing Dynamic Partial Reconfiguration (DPR) and providing state of the art, tamper proof and security features. These components must be free of export control. The ambition of DEMETER is to benefit from experience acquired within the BRAVE project to support the development of the next generation of rad-hard FPGA (“NG-FPGA-ULTRA”) in 28nm or beyond.

Beyond aerospace, this technology will also be used for market segments dealing with harsh environment, including but not limited to:

  •     Avionics
  •     Automotive
  •     Transportation (trucks, railways)
  •     Energy

For SYSGO the goal is to have PikeOS available on such a board that will probably be the next generation after LEON4, with a larger market place that space only to reduce costs.

Visit the official DEMETER website to learn more about that project.