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FPGA Conference Europe

Hotel NH München Ost Conference Center

July 4 - 6

The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is Europe's leading specialist conference for programmable logic devices. The conference is addressing focusses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work.

In increasingly AI-driven cloud data centres, in telecommunications and many other high-performance applications, Field Programmable Gate Arrays (FPGA) have proven themselves as flexible and powerful accelerator solutions for a wide range of tasks.

At this year's event, one focus is on the energy efficiency of flexible logic devices. This applies in particular to small, low-power components that rely on special production techniques or deliberately have only a limited number of programmable cells.

Join our Presentation

DAY 1 - 4th of July - Track 4: Embedded

9:45 - 10:30 am | Level: Beginner

Integrated RTOS and Hypervisor Ecosystem for MPU and MMU-based Processors

Markets for heterogeneous SoC applications with functional Safety can be found in industrial automation, robotics, MRD-certified (Medical Device Regulation) technology, and numerous new mobility applications. The focus ranges from autonomous vehicles and smart construction and agricultural machinery to electromobility, rail transport and avionics. However, one of the biggest challenges of these SoC designs is the high cost of developing and maintaining such heterogeneous solutions. Therefore, an application development of the SoCs that is as integrated as possible is required, as this is the only way to achieve synergy effects which reduce NRE costs and make the development of optimally performance-balanced real-time systems more efficient.

For example, it can be a major challenge to operate the individual subsystems inference-free on such an SoC. This also applies to cache inferences in multi-core implementations. In the previous RTOS and real-time hypervisor landscape, there have been no truly homogeneous solutions for managing such heterogeneous SoC with MMU- and MPU-based controllers. Most OS vendors have developed smaller RTOSs for the controllers with MPU, which have completely different APIs than the RTOS for controllers with MMU.

The presentation shows a homogeneous RTOS and real-time hypervisor solution, significantly simplifying programming and payload balancing. The APIs for programming applications for processors with MMU or MPU are therefore virtually identical. Essentially, only the memory management API was adapted accordingly. However, the change of an application from an MMU-based to an MPU-based core complex can be handled in a short timeframe despite the different memory handling. Even more important is the advantage that code for both core variants (MMU and MPU) can be certified in a similar way. Upcoming certifications can therefore build on the existing SIL 4, DAL A and ASIL D certifications.

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