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RISC-V Madras Initiative

SYSGO takes Part in Thales RISC-V MADRAS Initiative

SYSGO, Safety

Together with Thales Research and Technology (TRT), SYSGO is now member of the RISC-V consortium at the highest level (platinum). RISC-V is an open instruction specification set for CPU architectures. It is a strong growing foundation for open hardware efforts and commercial products with more than 120 members. At the last summit in December 2018 more than 1000 people joined. The architecture itself is very MIPS like, but no license fees or royalties are needed. It is supposed to have less power consumption and better performance.

Thales is creating a whole eco-system around RISC-V from high-level software down to the physical foundries. The cooperation with industrial players and universities is fundamental. A lot of hardware processors are not designed for functional safety. Time and space separation is only partially implemented and during the certification process a deterministic behaviour is important to get all artefacts in place.

In this strong growing community SYSGO will drive initiatives on functional Safety and will technically support the open source MADRAS project together with TRT and IITM (INDIAN INSTITUTE OF TECHNOLOGY MADRAS). The main output of the collaboration with IIT Madras, will be a definition of what is needed from a safety perspective and how this can be made available in other implementations. Evaluation and prototyping will be done to verify the functional impact on hardware and software. Finally, SYSGO will bring in its large experience in certification of embedded systems, the connection to accreditation authorities and helps to set up the system and design in a way that certification to the highest safety levels becomes realistic.

Read the Press Release