PikeOS offers strict partitioning and strong separation to provide built-in Security by design.
Extreme flexibility provides independence from suppliers in the choice of hardware architectures.
Use of COTS
The benefit of using Commercial-Off-The-Shelf (COTS) components is to lower overall costs for applications.
+80% of the original code base makes the available PikeOS documentation and certification artefacts reusable.
PikeOS instances on different cores can communicate with each other via message-based communication channels.
As an European company, our products have no export restrictions and are therefore ITAR free.
PikeOS for MPU
PikeOS for MPU is aiming to provide a safe and secure execution environment for medium-sized hardware platforms which do not provide a Memory Management Unit (MMU) and therefore cannot run the standard PikeOS.
PikeOS for MPU is intended to be used on MPU-based SoCs as well as on heterogeneous SoC implementing MMU and MPU clusters.
There is almost no learning curve, as the development tools and API stay nearly identical. PikeOS for MPU is embedded into CODEO as if it was just another architecture. That also makes migration from older applications remarkably simple. PikeOS Classic and PikeOS for MPU projects can even be managed in the same IDE at the same time.
Since the development tools, such as the ROM-Image builder and the VMIT (Virtual Machine Initialization Table) builder, are shared between the two operating systems, PikeOS for MPU inherits the qualification status of its bigger brother. That together with the fact that PikeOS for MPU bases on SYSGO's well-proven virtualization technology, PikeOS for MPU comes with a head start in terms of certification.
Multi-core processors have entered the embedded market. However, unlike to desktop computing where all processor cores are of the same type, embedded SoCs (Systems-on-a-Chip) are highly specialized for a dedicated purpose. Therefore, you will often find heterogeneous processor cores on the same chip.
With the PikeOS family of products, you can manage the entire software stack of such a complex big SoC within one single CODEO workspace. The project wizards and editors support you while you are planning the architecture of AMP and SMP domains. Even anything in between can be designed. A typical setup on a Xilinx Ultrascale+ would look like as shown in figure 1: PikeOS running multiple partitions on the Cortex-A53 cores in SMP mode, while the Cortex-R5 cores are executing PikeOS for MPU in AMP mode.
During your development it might turn out that the current assignment of software applications to processor cores is not optimal. Fortunately, this can be fixed with almost no efforts, as the PikeOS solution allows you to utilize the same API, no matter whether the CPU provides an MMU or MPU.
We provide two types of product support: The Standard Support covers the basic questions on the product use (installation, tools usage etc.) via E-Mail. The Premium Support offers more customer-specific help with direct contact to a dedicated support engineer.
Life Cycle Updates
Customers can benefit from ongoing improvements by accessing the SYSGO customer portal, where the latest updates of target binaries, new Board Support Packages, and add-ons are available.
Training & Consulting
We want to make building your target devices as convenient as possible. However, SYSGO’s guided trainings boost the skills of your embedded developer team and maximizes the output – for efficient teams that love to develop for embedded devices.
PikeOS for MPU
Starting into the Multi-Core World
PikeOS for MPU is based on the same time- and resource partition management as the classic PikeOS operating system. It also shares the same internal, fine-grained locking mechanisms and has the same means to mitigate hardware interference between processor cores, e.g. due to cache contention. The system integrator has all methods at his disposal to determine the worst-case execution times and enforce that any application does not consume more processor usage than it is allowed. Together with our partner eco system, PikeOS for MPU is ready for Safety-related standards on multi-core processors, such as CAST-32A.
PikeOS in Space
Reducing Single Event Upset (SEU) Effects
The environment in space is harsh, not only in terms of temperature and vibration, but also due to cosmic radiation. One of the major goals is to reduce and mitigate the effects of a single event upset. That is why hardware for space missions is stripped down in complexity. Boards based on processors without an MMU are way less complex, easier to understand and better to protect. We are proud to say that one of the first projects and our motivation to build PikeOS for MPU lies in the support of Space missions.
Certifiable MPU and MMU Cores
When using heterogeneous SoC (Systems-on-a-Chip) customers can profit from one PikeOS IDE for the configuration of certifiable MPU and MMU cores
Avionics customers can benefit from the ARINC 653, Part 1 compliant configuration
PikeOS for MPU supports less complex hardware which mitigates SEU effects. Great for SPACE applications
Support for systems with heterogeneous processor core such as the Xilinx Ultrascale+ which is widely used within the Automotive market
Safety & Security Bulletins / Patches
PikeOS for MPU offers Safety & Security bulletins / patches. Step by step, we enlarge Security add-on technologies, such as TSL, SSL or encryption libraries to help making systems more secure
PikeOS Native API
Enhanced PikeOS native API allows migration from software running on proprietary operating systems as well as usage of open-source projects
Less export compliance issues with PikeOS and PikeOS for MPU