As the European Union steps up its pursuit of technological sovereignty in critical microelectronics, open-source architectures—specifically RISC-V—have moved to the center of high-performance and safety-critical computing. The TRISTAN project (Together for RISc-V Technology and ApplicatioNs, Horizon Europe / Chips JU Grant #101095947), which concluded in June 2026, served as a major initiative to industrialize RISC-V across Europe.
SYSGO played a key role in TRISTAN by bridging open hardware designs with strict safety and security requirements.
The Technical Challenge: Determinism & Safety on Open Hardware
Deploying mixed-criticality workloads (e.g., executing flight control logic alongside telemetry analytics) on multicore RISC-V processors introduces significant integration challenges:
- Shared Resource Contention: Uncontrolled cache access and memory bus interference can degrade hard real-time guarantees.
- Lack of Hardware Virtualization Maturity: Early RISC-V implementations lacked standardized hypervisor extensions capable of isolating safety-critical tasks from rich operational software.
- Certification Gap: Bridging open-source cores to functional safety standards such as ISO 26262 (Automotive) or DO-178C (Avionics) requires a certifiable software baseline.
SYSGO’s Contribution:
PikeOS & ELinOS on the RISC-V CVA6: We have successfully ported the PikeOS hypervisor to the 64-bit CVA6 core. To demonstrate its mixed-criticality capabilities, our setup runs ELinOS in one partition while executing a PikeOS native application in a separate partition.
Trace Ingress Port Development: Working alongside with Thales and the University of Bologna for the TRISTAN project, we developed a Trace Ingress Port (TIP) for the CVA6 to facilitate advanced hardware tracing.
Outcomes & Demonstrators
SYSGO successfully validated two major industrial use cases under TRISTAN:
- Cloud-Connected Automotive Workloads: In collaboration with Aicas, evaluated real-world automotive telemetry and CAN trace workloads on a CVA6-based RISC-V FPGA platform to assess its readiness for industrial deployments.
- Smart Energy Edge Management: Validated OpenEMS and Apache StreamPipes energy orchestration software on top of PikeOS/ELinOS.
- Trace-FS Demonstrator: Demonstrated the hardware trace interface on the RISC-V CVA6 core, successfully capturing execution data.
Key Publications & Resources
- RISC-V Summit Europe (June 2026): "Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study"
- ERTS Conference (2026): "Porting OpenEMS and Apache StreamPipes Energy Management on RISC-V"
- EU CORDIS Repository: Grant Agreement #101095947
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