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SYSGO @ RISC-V Summit Europe 2024

Events & Webcasts, R&T Projects
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SYSGO will be at the RISC-V Summit Europe 2024 in Munich on June 24 - 28, 2024, and presenting our paper based on work in the TRISTAN and ISOLDE Chips JU projects.

Talk to our SYSGO experts at Poster Stand B-08 at Wednesday, June 26th.

Explorative Surveying RISC-V Open Hardware and Specifications for Mixed-Critical Systems

Mixed-critical systems, on which applications of varying criticality share hardware resources, are crucial in modern computing. This paper examines the robustness and implementation of mechanisms for such systems using RISC-V specifications and open hardware, specifically the CVA6 processor and OpenPiton SoC. It evaluates core-to-core communication, resource management, and components like performance counters, memory, and caches for mixed-criticality suitability. Additionally, the paper discusses future developments in mixed-critical systems using open hardware.


Mixed critical Systems on RISC-V Platforms

Download the Paper

More about the Projects

Other work in TRISTAN and ISOLDE covers making our embedded Linux ELinOS available for Linux, completing our PikeOS RISC-V offering, board support for the open-hardware CVA6 chip, TIP (Trace Ingress Port) support for CVA6, and demonstrations in automotive, space and smart home.

More about PikeOS at

More about ELinOS at