Back to the Overview

PikeOS for MPU: Xilinx Webcast about utilization of heterogenous processor environments

Use of MPU-based Controllers in heterogeneous SoC

Events & Webcasts, PikeOS
Please accept functional cookies to watch this video.

For many decades, multi-core processors have been present in desktop computers. The same transformation happened within the embedded market recently. The reasons are manifold, but mostly encouraged by requirements for performance and low-power; not to mention the availability of cost-efficient ARM processors (initially developed for the mobile phone market).

This progress does not stop in terms of Safety-critical systems, such as used in Automotive and Avionics. Those systems heavily depend on determinism, but the interferences and side effects between the processor cores account for additional complexity when it comes to the calculation of the worst-case execution times.

There is a difference to desktop computing where all processor cores are of the same type. Embedded SoCs (Systems-on-a-Chip) are often highly specialized for a dedicated purpose and these days you will find heterogeneous processor cores on the same chip. This makes development and certification difficult as a vast number of tools and tool-chains are required. Not to mention their qualification status which needs to be evaluated for almost all certification standards.

Embedded computing power alone does not control any aircraft or car. In real world scenarios you will need a whole lot of GPIOs (General Purpose Input/Output), field buses and networking protocols. The most adoptable solution is the usage of FPGAs (Field Programmable Gate Array) which also have the benefit of increased Safety.

Xilinx and SYSGO present a complete multi-core solution for the Safety-critical markets. Find guidance on how to

  • Choose the appropriate hardware for your Safety-critical system
  • Prevent and recover from Single Event Upset (SEU)
  • Design and architect systems that are compliant with the CAST-32a positioning paper
  • Run systems with processor cores with MMUs and MPUs at the same time
  • Solve inter core communication challenges
  • Use the same IDE and validated tools for diverse processor cores

Introducing PikeOS for MPU

PikeOS for MPU features the same API and development environment as the classic PikeOS, but now is available for much more light-weight CPUs that do not have a MMU (Memory Management Unit). The webcast concludes a demonstration that runs PikeOS and PikeOS for MPU side-by-side on a Xilinx Ultrascale+ SoC.

Watch the video on our YouTube channel:

More information at

# # #

Xilinx UltraScale