The Multi-Core Challenge: A practical Approach to CAST-32A & AMC 20-193 Compliance
Overcoming Challenges in Adopting Multi-Core Processors for Safety-Critical Applications
Our technical whitepaper gives insights into the complexities and solutions for integrating multi-core processors (MCPs) in safety-critical applications. MCPs offer enhanced computing power while maintaining a favorable Size, Weight, and Power (SWaP) profile, making them highly attractive to developers across various embedded sectors.
However, the adoption of MCPs in safety-critical, hard real-time applications presents unique challenges. Unlike single-processor applications, finding an optimal schedule for multiple tasks on multiple cores to meet stringent deadlines is not efficiently solved by an algorithm alone. Guaranteeing Worst-Case Execution Time (WCET) requires imposing certain usage restrictions.
Furthermore, the sharing of hardware resources in MCPs can introduce hardware interference, particularly in areas like shared hierarchical memory. This interference leads to a widened distribution of execution times, eroding the tight peak and resulting in longer tails. Critical resource sharing, such as L2 cache and memory subsystems, can adversely impact software execution times, potentially leading to unsafe failure conditions.
In our whitepaper, we address these challenges and explore innovative solutions for adopting MCPs in safety-critical applications. We discuss techniques to ensure Worst-Case Execution Time, mitigate hardware interference, and maintain system safety and reliability.