Back to the Overview

The Multi-Core Challenge: A practical Approach to Cast-32A & AMC 20-193 Compliance

Events & Webcasts, Avionics & Defense

Concerns over the suitability of Multi-Core Processors (MCPs) for safety-critical applications are nothing new, however they offer huge benefits in Size, Weight and Power (SWaP) improvements. CAST-32A seeks to provide guidance in the use of MCPs in avionics, where robust partitioning between domains is critical. This can be realised using an RTOS, separation kernel, or hypervisor, however hardware interference still represents a challenge.

For a single core, the calculation of Worst-Case Execution Times (WCET) through static analysis alone can only ever be an approximation. In an MCP environment, shared resources such as memory and caches further degrade the calculation of WCET, making measurement essential.

Measurement of WCET allows the identification of sequences of code that have demanding execution paths in the tool operational environment, giving accurate constraints to satisfy CAST-32A objectives.

This webcast presents a turnkey solution from SYSGO and LDRA designed to meet the objectives of CAST-32A within the context of a DO-178C compliant project. Many of these best practices also apply to Avionics, Automotive, Medical, Industrial and Railway use cases.


The Webcast discusses

  • Appropriate static analysis techniques
  • Compliance with coding standards
  • Using an integrated tool suite to make on-target testing an integral part of the test process and how this enables the measurement of WCET
  • How automated traceability to evidential artefacts can relieve a typical project management pain point, when tests fail


Key Takeaways

  • The importance of operating system selection to the certification process
  • The significant features of an optimal OS, hypervisor layer and the importance of robust partitioning
  • Preparation requirements for CAST-32A compliance
  • Automated traceability to standards objectives and project requirements
  • How static analysis and MISRA compliance are achieved, and their impact on maintainability
  • Code analysis and execution on the hardware target through the OS IDE
  • Measurement and optimization of WCET through dynamic analysis
  • Collation of statement, branch decision and MC/DC coverage on MCDs
  • The significance of data and control coupling


More information at www.sysgo.com/avionics

More information at www.ldra.com